The present disclosure relates to a structure including a plurality of stacked semiconductor devices, and each of the semiconductor devices of the structure.
In recent years, with the increasing miniaturization of electronic devices, it is strongly desirable to reduce the size of semiconductor devices loaded or mounted thereon and to increase the density of such semiconductor devices. Accordingly, a recent trend is to use a package called a ball grid array (BGA) in which external terminals are arranged in a lattice pattern on an entire lower surface of a semiconductor device, or to use a package called a chip size package (CSP) in which external terminals are arranged with smaller pitch than that in BGA and which has a smaller size than that of BGA.
Meanwhile, in recent years, to further reduce the size of semiconductor devices and increase the density thereof, a stacked package having a structure in which the above-described CSPs are stacked is used in many cases. Such stacked packages are generally called package on package (PoP), and becoming to be used as a major method of achieving high-density packaging. In stacked packages, an electrode is provided on an upper surface of a lower package, and thus, stacking packages is allowed. Therefore, various configurations based on the known package configurations have been devised.
For example, a configuration (see, for example, U.S. Pat. No. 4,086,657) in which a semiconductor element is mounted by a flip chip process and staking packages is allowed by taking advantage of the feature of the configuration employing flip chip packaging that the height of each package is small, and a configuration (see, for example, U.S. Pat. No. 4,022,405) in which a connection height between packages is made as small as possible to allow stacking packages using a flip chip structure and a cavity structure have been proposed.